This patent application claims priority based on a Japanese patent application, H10-176460 filed on Jun. 23, 1998 the contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a signal output apparatus capable of outputting a differential signal, and more particularly to a signal output apparatus which outputs a differential signal in a semiconductor device testing apparatus to a test semiconductor device.
2. Description of Related Art
FIG. 1 shows a conventional semiconductor device testing apparatus which generates a differential signal in a semiconductor device using two signal output units. The semiconductor device testing apparatus has a formatter 20 and a differential output circuit 30. The formatter 20 has multiple formatter elements. The differential output circuit 30 has multiple differential output circuit elements. The formatter element 20a and the differential output circuit element 34a constitute the first signal output Unit. The differential output circuit element 34a has a pin driver 80a, and switches 82a and 84a. The formatter element 20b and the differential output circuit element 34b constitute the second signal output unit. The differential output circuit element 34b has a pin driver 80b, and switches 82b and 84b. As shown in the drawing, the first signal output unit and the second signal output unit are identically structured.
The semiconductor device testing apparatus is separated into a testing apparatus main body which generates a semiconductor device input signal to be input to the test semiconductor device and a test head for loading and testing the test semiconductor device. In the conventional apparatus for generating a differential signal shown in FIG. 1, the formatter 20 is contained in the testing apparatus main body and the differential output circuit 30 is contained in the test head. The cables 60a and 60b connect the testing apparatus main body with the test head.
The formatter element 20a re-shapes the signal waveform of the semiconductor device input signal 12a so as to input the semiconductor device input signal 12a to the test semiconductor device. The formatter element 20b re-shapes the signal waveform of the semiconductor device input signal 12b to input the semiconductor device input signal 12b to the test semiconductor device. The waveform re-shaped semiconductor device input signal 22a as a differential signal is then input to the pin driver 80a. The waveform reshaped semiconductor device input signal 22b as a differential signal is then input to the pin driver 80b. The pin driver 80a outputs the first signal 32a and the pin driver 80b outputs the second signal 32b. The second signal 32b has an inverted pattern of the first signal 32a. 
The switches 82a and 84a are selectively opened and closed. The switches 82b and 84b are also selectively opened and closed. When the switches 82a and 82b are closed, the first signal 32a and the second signal 32b are transmitted to the test semiconductor device. When the switches 84a and 84b are closed, the earth electric potential is supplied to the test semiconductor device.
In the conventional semiconductor device testing apparatus, in testing the differential signal pin set, a differential signal is generated using the first signal 32a and the second signal 32b, which are two independent signals.
When differential signals are generated using the conventional semiconductor device testing apparatus shown in FIG. 1, the skew between the differential signals becomes large. That is, the first signal output unit and the second signal output unit output the first signal 32a and the second signal 32b, respectively, independently of each other. Therefore, the skew between the differential signal made by the first signal and the differential signal made by the second signal 32b contains at least the skew between the signals generated by the formatters 20a and 20b and the skew between the signals generated by the pin drivers 80a and 80b. 
This skew between the differential signals causes an operation error in the semiconductor device being tested. The skew between the differential signals input to the test semiconductor device hence must be reduced as much as possible.
To solve the problem stated above, the present invention provides a semiconductor device testing apparatus for testing a semiconductor device having a differential signal input pin set to which a differential signal is input. This semiconductor device testing apparatus has a pattern generator for generating a semiconductor device input signal for testing the semiconductor device, a differential signal separation driver which receives the semiconductor device input signal and outputs the semiconductor device input signal as a differential signal to the differential signal input pin set through two separate transmission lines, a semiconductor device plug-in unit, to which the semiconductor device is plugged in, for supplying the differential signal output from the differential signal separation driver to the semiconductor device, and an output signal detection unit which detects an output signal that is generated based on the differential signal supplied to the semiconductor device by the semiconductor device plug-in unit.
The differential signal separation driver may be installed for each differential signal input pin set of the semiconductor device. The semiconductor device testing apparatus may further have a formatter for re-shaping the waveform of the semiconductor device input signal generated by the pattern generator. The semiconductor device input signal input to the differential signal separation driver may be a differential signal.
The present invention also provides a signal output apparatus having a selection circuit which receives a first signal and a second signal and selects and outputs the inverted first signal as an invert signal of the first signal or the second signal, a first driver for outputting the first signal, and a second driver for outputting the inverted first signal or the second signal selected by the selection circuit.
The signal output apparatus may further have a first formatter for generating the first signal and a second formatter for generating the second signal. The signal output apparatus may further have a time delay circuit for delaying the first signal.
The time delay circuit may delay transmission of the first signal by a length of time substantially equal to the length of time the inverted first signal and the second signal require to pass through the selection circuit. The first formatter may re-shape the waveform of the first signal in generating the first signal and the second formatter may re-shape the waveform of the second signal in generating the second signal.
Moreover, the present invention provides a semiconductor device testing apparatus for testing a semiconductor device having a differential signal input pin set to which a differential signal is input, having a pattern generator for generating a semiconductor device input signal for testing the semiconductor device, a signal output circuit which outputs the semiconductor device input signal generated by the pattern generator to the semiconductor device, a semiconductor device plug-in unit, to which the semiconductor device is plugged in, for supplying the semiconductor device signal output from the signal output circuit to the semiconductor device, and an output signal detection unit which detects an output signal that is generated based on the semiconductor device input signal supplied to the semiconductor device by the semiconductor device plug-in unit. In this case, the signal output circuit has a selection circuit which receives a first signal and a second signal and selects and outputs the inverted first signal as an invert signal of the first signal or the second signal, a first driver for outputting the first signal, and a second driver for outputting the inverted first signal or the second signal selected by the selection circuit.
In one aspect of the present invention, the signal output circuit may further have a first formatter for generating the first signal and a second formatter for generating the second signal. The signal output circuit may further have a time delay circuit for delaying the first signal.
The time delay circuit may delay transmission of the first signal by the length of time substantially equal to the length of time the inverted first signal and the second signal require to pass through the selection circuit. The first formatter may re-shape the waveform of the first signal in generating the first signal and the second formatter re-shapes the waveform-of the second signal in generating the second signal.